Phase-locked loops (PLLs) are widely used in processor systems, communications systems, and signal processing systems, among others. PLLs are used for generating clock signals with various desired frequencies which are capable of being provided to a processor for running its internal logic. Processors derive their timing from these clock signals and the frequency of a processor's clock signal dictates the speed of execution of operational instructions by a processor.
Because the speed of execution of operational instructions may be adjusted by adjusting the frequency of the clock signal provided to the processor, there exists a proportional relationship between a processor's clock frequency and the processor's power consumption. A higher clock frequency results in a processor executing more instructions per unit of time and, therefore, the electrical circuitry and logic of this processor draw more current from its power source and dissipate more energy in the form of thermal energy.
PLLs are used to regulate speed of execution, power consumption, and heat dissipation of these processors. Therefore, managing power consumption in a processor system can be performed by managing the frequency of the output clock of the PLL in the processor system.
During the course of managing power consumption in a processor system, it is often required that power consumption be reduced considerably in a short amount of time, thereby necessitating an abrupt reduction of a PLL's output clock frequency to a new desired frequency that is much less than the current operating frequency. An example of this arises in a situation where a mobile phone's battery is low. The phone's user has just closed a computationally extensive application that required all the computational resources of the mobile phone's processor at the processor's maximum operating frequency, and then the user opens an application that requires few computational resources. In this example, as it is no longer necessary for the mobile phone's processor to operate at its maximum operating frequency, a power management unit of the mobile phone may want to considerably reduce the operating frequency of the processor in order to conserve battery power. Conversely, and in other situations, the operating frequency of the processor may need to be increased to accommodate for an increased workload.
In either event, the magnitude of the change in frequency and how quickly this change needs to take effect are two important considerations in PLLs. It is undesirable to suddenly change the output frequency to a new frequency that is very different from the current frequency, as this abrupt change will result in the processor immediately drawing more current at a much higher rate than before. This sudden change in current consumption results in a transient effect across the processor system's power supply network in what is known in the art as a di/dt effect or a load step. Furthermore, extreme changes in frequency are associated with a higher likelihood of resulting in a frequency overshoot or undershoot, in which case the processor will be operating at a different clock frequency than desired.
To counteract these problems, coarse-stepping to the new desired clock frequency may be performed. Although coarse-stepping alleviates some of the frequency overshoot or undershoot problems, coarse-stepping causes delay in reaching the new desired clock frequency. This delay is not only attributed to the inherent delay of achieving a desired frequency in many coarse steps (as opposed a single large step), but is also attributed to communication and handshake delays that occur when programming or commanding a PLL to coarse-step its frequency output, particularly when the communication is done across an asynchronous interface.
It is, therefore, desirable to have a method and apparatus to adjust the output frequency of a PLL without incurring significant delay, while at the same time minimizing the likelihood of a frequency overshoot and undershoot and load step.